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Preliminary Technical Data
FEATURES
SNR = 60 dBFs @ fIN up to 70 MHz @ 250 MSPS ENOB of 9.7 @ fIN up to 70 MHz @ 250 MSPS (-0.5 dBFS) SFDR = 80 dBc@ fIN up to 70 MHz @ 250 MSPS (-0.5 dBFS) Excellent Linearity DNL = 0.3 LSB (Typical) INL = 0.5 LSB (Typical) LVDS at 250 MSPS (ANSI-644 levels) 900 MHz Full Power Analog Bandwidth On-Chip Reference and Track-and-Hold Power Dissipation = 380 mW Typical @ 250 MSPS 1.25 V Input Voltage Range 1.8 V Analog Supply Operation Output Data Format Option Data Clock Output Provided Clock Duty Cycle Stabilizer
10-Bit, 170/200/250 MSPS 1.8 V A/D Converter AD9211
AGND AVDD (1.8V) DrVDD (1.8V) DGND (Pin 0) ADC 10 10-bit Core Output 10 Staging LVDS D9-D0 (D4-D0 DDR mode) OTR+ OTRSerial Port DCO+ DCORESET SCLK SDIO CSB
AD9211
Ref VIN+ VINT/H
CLK+ CLK-
Clock Mgmt
Figure 1. Functional Block Diagram
APPLICATIONS
Wireless and Wired Broadband Communications Cable Reverse Path Communications Test Equipment Radar and Satellite Subsystems Power Amplifier Linearization
Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead chip scale package (56 LFCSP) specified over the industrial temperature range (-40C to +85C).
PRODUCT HIGHLIGHTS
1. 2. 3. High Performance--Maintains 60 dB SNR @ 250 MSPS with a 65 MHz input. Low Power--Consumes only 380mW @ 250 MSPS. Ease of Use--LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample/hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Supported DDR mode reduces number of output data traces Serial Port Control - Standard serial port interface supports various product functions such as data formatting, enabling a clock duty cycle stabilizer, power down, gain adjust and output test pattern generation. Pin compatible family - 12-bit pin compatible family offered as AD9230.
PRODUCT DESCRIPTION
The AD9211 is a 10-Bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format or gray code. A data clock output is available for proper output data timing.
4.
5.
Rev. PrA
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AD9211 TABLE OF CONTENTS
AD9211-Specifications.................................................................... 3 AC Specifications.............................................................................. 4 Digital Specifications........................................................................ 5 Switching Specifications .................................................................. 6 Absolute Maximum Ratings1 .......................................................... 7 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Terminology .................................................................................... 10 Equivalent circuits .......................................................................... 12 Typical Performance CHARACTERISTICS ............................... 13 Theory of Operation .................................................................. 14 Analog Input and Reference Overview ................................... 14 Clock Input Considerations ...................................................... 15
Preliminary Technical Data
Power Dissipation and POWER DOWN Mode .................... 16 Digital Outputs ........................................................................... 17 Timing ......................................................................................... 17 RBIAS........................................................................................... 18 AD9211 Configuration Using the SPI ..................................... 18 Hardware Interface..................................................................... 19 Reading the Memory Map Table.............................................. 19 Open Locations .......................................................................... 19 Default Values ............................................................................. 19 Logic Levels................................................................................. 19 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
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Preliminary Technical Data AD9211-SPECIFICATIONS
AD9211
Table 1. DC SPECIFICATIONS (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = -40C, TMAX = +85C, fIN = -0.5 dBFS, Internal Reference, Full Scale = 1.25 V, DCS Enabled, unless otherwise noted.)
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error ANALOG INPUTS (VIN+, VIN-) Differential Input Voltage Range Input Common-Mode Voltage Input Resistance (differential) Input Capacitance POWER SUPPLY (LVDS Mode) AVDD DRVDD Supply Currents IANALOG(AVDD = 1.8 V) 1 IDIGITAL (DRVDD = 1.8 V)3 Power Dissipation3 Power Supply Rejection Temp Min AD9211-170/-200 Typ 10 Guaranteed TBD TBD 0.3 0.3 0.5 0.5 TBD TBD Max Min AD9211-250 Typ 10 Guaranteed TBD TBD 0.3 0.3 0.5 0.5 TBD TBD Max Unit Bits
Full 25C 25C 25C Full 25C Full Full Full
mV % FS LSB LSB LSB LSB V/C %/C
Full Full Full 25C Full Full Full Full Full 25C 1.7 1.7
1.25 1.3 4 2 1.8 1.8 122/138 50/50 310/340 TBD 1.9 1.9 1.7 1.7
1.25 1.3 4 2 1.8 1.8 151 60 380 TBD 1.9 1.9
V V k pF V V mA mA mW mV/V
1 IAVDD and IDRVDD are measured with a dc input at rated Clock rate. See Typical Performance Characteristics and Applications sections for IANALOG and IDRVDD with dynamic input vs clock rate
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AD9211 AC SPECIFICATIONS1
Preliminary Technical Data
Table 2. (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = -40C, TMAX = +85C, fIN = -0.5 dBFS, Internal Reference, Full Scale = 1.25 V, Ain = -0.5dBFS, DCS Enabled unless otherwise noted.)
Parameter SNR fin=10 MHz fin=70 MHz fin=100 MHz fin=240 MHz SINAD fin=10 MHz fin=70 MHz fin=100 MHz fin=240 MHz EFFECTIVE NUMBER OF BITS (ENOB) fin=10 MHz fin=70 MHz fin=100 MHz fin=240 MHz WORST HARMONIC (2nd or 3rd) fin=10 MHz fin=70 MHz fin=100 MHz fin=240 MHz WORST HARMONIC (4th or Higher) fin=10 MHz fin=70 MHz fin=100 MHz fin=240 MHz TWO-TONE IMD2 F1, F2 @ -7 dBFS ANALOG INPUT BANDWIDTH 25C Full 25C Full 25C 25C 60 59.5 60 59.5 58.5 57.5 60 59.5 60 59.5 58.5 57.5 dB dB dB dB dB dB Temp Min AD9211-170/-200 Typ Max Min AD9211-250 Typ Max Unit
25C Full 25C Full 25C 25C
60 60 60 60 59 58
60 60 60 60 59 58
dB dB dB dB dB dB
25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C
9.6 9.6 9.6 9.6 9.4 9.2 -80 -80 -80 -80 -78 -75
9.6 9.6 9.6 9.6 9.4 9.2 -80 -80 -80 -80 -77 -75
Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc
25C Full 25C Full 25C 25C 25C 25C
-85 -85 -85 -85 -83 -78 -75 900
-85 -85 -85 -85 -83 -78 -75 900
dBc dBc dBc dBc dBc dBc dBc MHz
1 2
All ac specifications tested by driving CLK+ and CLK- differentially. F1 = 28.3 MHz, F2 = 29.3 MHz.
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Preliminary Technical Data DIGITAL SPECIFICATIONS
Table 3 (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = -40C, TMAX = +85C, DCS Enabled unless otherwise noted.)
Parameter CLOCK INPUTS Differential Input Voltage1 Common-Mode Voltage2 Input Resistance Input Capacitance LOGIC INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current Logic 0 Input Current Input Capacitance LOGIC OUTPUTS3 VOD Differential Output Voltage VOS Output Offset Voltage Output Coding Temp Min AD9211-170/-200 Typ Max Min AD9211-250 Typ Max
AD9211
Unit
Full Full Full 25C Full Full Full Full 25C Full Full
tbd tbd tbd 4 .8 x VDD .2 x AVDD 10 10 4 247 454 1.125 1.375 Twos Complement, or Binary
tbd tbd tbd 4 2.0 0.8 10 10 4 247 454 1.125 1.375 Twos Complement, or Binary
V V k pF V V A A pF mV V
1 2 3
All ac specifications tested by driving CLK+ and CLK- differentially, |(CLK+)- (CLK-)| > 200 mV. Clock inputs' common mode can be externally set, such that xx.xV < (Clk+ or Clk- ) < zzz V. LVDS RTermination = 100
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AD9211 SWITCHING SPECIFICATIONS
Preliminary Technical Data
Table 4. (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = -40C, TMAX = +85C, DCS Enabled unless otherwise noted.)
Parameter (Conditions) Maximum Conversion Rate1 Minimum Conversion Rate CLK+ Pulsewidth High (tEH) CLK+ Pulsewidth Low (tEL) OUTPUT (LVDS) Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tPD- tCPD) Latency (L) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out of Range Recovery Time
1 1 1
Temp Full Full Full Full Full Full 25C 25C Full Full Full 25C 25C 25C
Min 170/200 TBD TBD TBD
AD9211-170/-200 Typ Max 40
Min 250 TBD TBD TBD
AD9211-250 Typ Max 40
Unit MSPS MSPS ns ns ns ns ns ns ns ns Cycles ns ps rms Cycles
3.9 0.4 0.4 3.2 TBD 5 TBD 0.2 TBD
3.9 0.4 0.4 3.2 TBD 5 TBD 0.2 TBD
1
All ac specifications tested by driving CLK+ and CLK- differentially.
N-1 N
tA
N+L+1
N+L+2
N+L+3
AIN N+1 L CYCLES N+L
tEH
CLK+ CLK-
tEL
1/fS
tPD
DATA OUT N-L
tV
N-L+1 N N+1 N+2
tCPD
DCO+ DCO-
Figure 2. Timing Diagram (L=5 Cycles)
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS1
Parameter AVDD DRVDD Analog Inputs Digital Inputs REFIN Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature JA 2 Rating 2.0 V 2.0V -0.5 V to AVDD + 0.5 V -0.5 V to DRVDD + 0.5 V -0.5 V to AVDD + 0.5 V 20 mA -40C to +125C -65C to +150C 150C 150C TBDC/W
AD9211
1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 Typical JA = TBD C/W (heat slug soldered) for multilayer board in still air with solid ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD9211 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
DCODRGND
DNC DCO+
DRVDD
AVDD CLK46 45
56
55 54
53 52
51
50 49
48 47
D1D1+ D2D2+ D3D3+ DRVDD DRGND D4D4+ D5D5+ D6D6+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin 0 (exposed paddle) = AGND 15 16 17 18 19 20 21 22 23 24 25 26 27 28 AD9211 56 Lead for LF-CSP TOP VIEW (Not to Scale)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CLK+ AVDD
D0DNC
DNC DNC
D0+
AVDD AVDD CML AVDD AVDD AVDD VINVIN+ AVDD AVDD AVDD RBIAS AVDD PDN
OVR+ DRGND
(MSB) D9+ OVR-
DRVDD
D7+ D8-
D8+ D9-
D7-
SDIO SCLK
Figure 3. Pinout
Table 5. PIN FUNCTION DESCRIPTIONS
Pin Number 30,32,33,34,37,38,39,41, 42,43,46 7, 24,47 0 8, 23,48 35 36 40 44 45 31 28 25 26 27 29 49 50 51-54 55 56 Mnemonic AVDD DRVDD AGND1 DRGND1 VIN+ VIN- CML CLK+ CLK- RBIAS RESET SDIO SCLK CSB PWDN DCO- DCO+ DNC D0- D0+ Description 1.8 V Analog Supply. 1.8 V Digital Output Supply. Analog Ground. Digital Output Ground. Analog Input--True. Analog Input--Complement. Analog input common mode output pin Clock Input--True. Clock Input--Complement. Set Pin for Chip Bias Current. (Place 1% X kohm resistor terminated to ground). Chip Reset ( Active high) Serial port input/output pin Serial port clock Serial port chip select (Active low) Chip power down Data Clock Output--Complement. Data Clock Output--True. Do not connect D0 Complement Output Bit. D0 True Output Bit.
1
AGND and DRGND should be tied to a common quiet ground plane. Rev. PrA | Page 8 of 21
CSB RESET
Preliminary Technical Data
Pin Number 1 2 3 4 5 5 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Mnemonic D1- D1+ D2- D2+ D3- D3+ D4- D4+ D5- D5+ D6- D6+ D7- D7+ D8- D8+ D9- D9+ OTR- OTR+ Description D1 Complement Output Bit. D1 True Output Bit. D2 Complement Output Bit. D2 True Output Bit. D3 Complement Output Bit. D3 True Output Bit. D4 Complement Output Bit. D4 True Output Bit. D5 Complement Output Bit. D5 True Output Bit. D6 Complement Output Bit. D6 True Output Bit. D7 Complement Output Bit. D7 True Output Bit. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit. D9 True Output Bit. Overrange Complement Output Bit. Overrange True Output Bit.
AD9211
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AD9211 TERMINOLOGY
Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the Clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Crosstalk Coupling onto one channel being driven by a low level (-40 dBFS) signal when the adjacent interfering channel is driven by a fullscale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range
Preliminary Technical Data
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
PowerFULLSCALE
V2 FULLSCALE RMS = 10 log Z INPUT 0.001

Gain Error
The difference between the measured and ideal full-scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
Minimum Conversion Rate
The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. Peak-to-peak differential is computed by rotating the input's phase 180 and again taking the peak measurement. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) Calculated from the measured SNR based on the equation
The Clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The Clock rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of CLK+ and CLK- and the time when all output data bits are within valid logic levels.
ENOB =
SNR MEASURED - 1.76dB 6.02
Noise (for Any Range within the ADC)
Calculated as follows:
- SNRdBc - SignaldBFS FS VNOISE = Z x 0.001 x 10 dBM 10
Clock Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time the Clock pulse should be left in low state. At a given clock rate, these specifications define an acceptable Clock duty cycle.
where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value of the particular input level, and Signal is the signal level within the ADC
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Preliminary Technical Data
reported in dB below full scale. This value includes both thermal and quantization noise.
Power Supply Rejection Ratio
AD9211
of the worst third-order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc.
Transient Response Time
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
The ratio of the rms value of either input tone to the rms value
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AD9211 EQUIVALENT CIRCUITS
AVDD AVDD
Preliminary Technical Data
AVDD
AVDD
DRVDD
Vcm
CLK+ 10k 10k CLK-
V+ DataoutV-
V- Dataout+ V+
Figure 4 Clock Inputs
Figure 7. Data Outputs (LVDS Mode)
AVDD VIN+
BUF
.
AVDD 1000
BUF
AVDD VIN-
1000
BUF
Figure 5. Analog Inputs (VX=~ 1.3V)
AVDD
AVDD
IN
Figure 6. Logic Inputs
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Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
TBD
AD9211
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AD9211
THEORY OF OPERATION
The AD9211 architecture consists of a front-end sample and hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 10-Bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state.
1V p-p 49.9
Preliminary Technical Data
499 33 499 AVDD VIN+
AD8138
0.1F 523 499
20pF 33
AD9211
VIN - CML
05491-004
Figure 8. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9211. This is especially true in IF under-sampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9211 is a differential buffer. For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common mode settling errors are symmetrical. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a single-ended signal.
1.25V p-p 49.9
33 10pF 33
VIN+
AD9211
VIN-
A wideband transformer, such as Mini-Circuits' ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 1.3 V. An internal differential voltage reference creates positive and negative reference voltages that define the 1.25Vp-p fixed span of the ADC core. This internal voltage reference can be adjusted by means of SPI control. See SPI control section for more details.
0.1F
05491-005
Figure 9. Differential Transformer--Coupled Configuration
Single-Ended Input Configuration
A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 10 details a typical single-ended input configuration.
Differential Input Configurations
Optimum performance is achieved while driving the AD9211 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2+0.5V, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
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Preliminary Technical Data
10F R 1.25Vp-p 49.9 0.1F AVDD VIN+
150
AD9211
AD9211
VINCML AGND 0.1uF
0.1uF 150 PECL
CLK+
AD9512
0.1uF
AD9230
CLK-
Figure 10. Single-Ended Input Configuration using SPI enabled CML function
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9211 the sample clock inputs (CLK+ and CLK-) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK- pins via a transformer or capacitors. These pins are biased internally and require no additional bias (See Figure X).
AVDD
Figure X. Differential PECL Sample Clock for AD9230/AD9211
1.2V CLK+ 2pF CLK2pF
Figure .Equivalent Clock Input Circuit
Figure X shows one preferred method for clocking the AD9211. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD9211 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9211 while preserving the fast rise and fall times of the signal, which are critical to a low jitter performance.
CLK+ Clock Source CLK-
AD9230
Figure X. Transformer Coupled Differential Clock for AD9230/AD9211
If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure X. The AD9512 (or same family) from offers excellent jitter performance.
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AD9211
Clock Input Considerations
Preliminary Technical Data
AD9211. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9211 contains a DCS (duty cycle stabilizer) that retimes the non-sampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9211. Noise and distortion performance are nearly flat for a wide range duty cycles with the DCS on. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the non-sampling edge. As a result, any changes to the sampling frequency require approximately TBD clock cycles to allow the DLL to acquire and lock to the new rate.
POWER DISSIPATION AND POWER DOWN MODE
As shown in Figure 12 and Figure 14, the power dissipated by the AD9211 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated by
SNR = 20 log f INPUT x t J 2
In the equation, the rms aperture jitter represents the rootmean square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. IF under-sampling applications are particularly sensitive to jitter, see Figure 11.
75 0.2ps 70
Figure 12. AD9211-170, Supply Current vs. fSAMPLE for fIN = 10.3 MHz
65 0.5ps SNR (dBc) 60 1.0ps 1.5ps 2.0ps 2.5ps 3.0ps 45
55
Figure 13. AD9211-200, Supply Current vs. fSAMPLE for fIN = 10.3 MHz
50
40 1 10 100 INPUT FREQUENCY (MHz) 1000
Figure 11. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the
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Preliminary Technical Data
AD9211
The format of the output data is offset binary. An example of the output coding format can be found in Table 7.
Table 7. Digital Output Coding
Code 1024 512 511 0 (VIN+) - (VIN-), Input Span = 1.252 V p-p (V) 1.000 0 -0.000488 -1.00 Digital Output Offset Binary (D9 ... D0) 11 1111 1111 10 0000 0000 01 1111 1111 00 0000 0000
As detailed in Interfacing to ADC SPI, the data format can be selected for either offset binary or twos complement, or Gray code (SPI access only).
Figure 14. AD9211-250, Supply Current vs. fSAMPLE for fIN = 10.3 MHz
Out-of-Range (OTR)
An out-of-range condition exists when the analog input voltage is beyond the input range of the ADC. OTR is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. Thus, OTR has the same pipeline latency as the digital data. OTR is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range as shown in Figure 15. OTR will remain high until the analog input returns to within the input range and another conversion is completed. By logically AND-ing OTR with the MSB and its complement, over-range high or under-range low conditions can be detected.
By asserting the PDWN pin high, the AD9211 is placed in standby mode. In this state, the ADC typically dissipates 1 mW even if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9211 into its normal operational mode. An additional stand by mode is supported by means of varying the clock input. When the clock rate falls below 20MHz, the AD9211 will assume a standby state. In this case, the biasing network and internal reference remain on but digital circuitry is powered down. Upon reactivating the clock, the AD9211 will resume normal operation after allowing for the pipeline latency.
DIGITAL OUTPUTS
The AD9228's differential outputs conform to the ANSI-644 LVDS standard on default power up. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9211's LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. It is recommended to keep the trace length no longer than 12 inches and to keep differential output traces close together and at equal lengths.
Figure 15. OTR Relation to Input Voltage and Output Data for AD9230/AD9211
TIMING
The AD9211 provides latched data outputs with a pipeline delay of five clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal.
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AD9211
The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9211. These transients can degrade the converter's dynamic performance. The AD9211 also provides data clock output (DCO) intended for capturing the data in an external register. The data outputs are valid on the rising edge of DCO. The lowest typical conversion rate of the AD9211 is 40 MSPS. At clock rates below 1 MSPS, the AD9211 will assume standby mode.
Spec Name tDS tDH tCLK tS tH tHI tLO
Preliminary Technical Data
Meaning Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state
RBIAS
The AD9211 requires the user to place a 10K resistor between the RBIAS pin and ground. This resister should have a 1% tolerance, and is used to set the master current reference of the ADC core.
AD9211 CONFIGURATION USING THE SPI
The AD9211 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space inside the ADC. This gives the user added flexibility to customize device operation depending on the application. Addresses are accessed (programmed or read back) serially in one-byte words. Each byte may be further divided down into fields which are documented in the Memory Map Section below. There are three pins that define the serial port interface or SPI to this particular ADC. They are the SPI SCLK / DFS, SPI SDIO / DCS, and CSB pins. The SCLK/DFS (serial clock) is used to synchronize the read and write data presented the ADC.. The SDIO / DCS (serial data input/output) is a dual purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB or chip select bar is an active low control that enables or disables the read and write cycles. See Table X.
Table X. Serial Port Pins
Pin SCLK SDIO Function SCLK (Serial Clock) is the serial shift clock in. SCLK is used to synchronize serial interface reads and writes. SDIO (Serial Data Input/Output) is a dual purpose pin. The typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame. CSB (Chip Select Bar) is active low controls that gates the read and write cycles. Master device reset. When asserted, device assumes default settings.
During an instruction phase a 16bit instruction is transmitted. Data then follows the instruction phase and is determined by the W0 and W1 bits which is 1 or more bytes of data. All data is composed of 8bit words. The first bit of each individual byte of serial data indicates whether this is a read or write command. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. Data may be sent in MSB or in LSB first mode. MSB first is default on power up and may be changed by changing the configuration register. For more information about this feature and others see SPI Doc at www.analog.com.
CSB RESET
The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing. An example of the serial timing and its definitions can be found in Figure X and Table X. Table X. SPI Timing Diagram specifications
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Preliminary Technical Data
HARDWARE INTERFACE
The pins described in Table X comprise the physical interface between the user's programming device and the serial port of the AD9211. All serial pins are inputs, which is an open-drain output and should be tied to an external pull-up or pull-down resistor (suggested value 10 k). This interface is flexible enough to be controlled by either PROMS or PIC mirocontrollers as well. This provides the user to use an alternate method to program the ADC other than a SPI controller. If the user chooses to not use the SPI interface, some pins serve a dual function and are associated with a specific function when strapped externally to AVDD or ground during device power on. The section below describes the strappable functions supported on the AD9211. AD9211
AD9211
configuration register map (Address 0x00 to Address 0x02), device index and transfer register map (Address 0x04 to Address 0x05, and Address 0xFF), global ADC function register map (Address 0x08 to Address 0x09), and flexible ADC functions register map (Address 0x0B to Address 0x25). The flexible ADC functions register map is product specific. Starting from the right hand column, the memory map register in Table X documents the default hex value for each hex address shown. The column with the heading Byte 7 (MSB) is the start of the default hex value giving. For example, hex address 0x14, flex_output_phase has a hex default value of 00h. This means Bit 3 = 0, Bit 2 = 0, Bit 1 = 1, and Bit 0 = 1 or 0011 in binary. This setting is the default output clock or DCO phase adjust option. The default value adjusts the DCO phase 90deg relative to the Nominal DCO edge and 180deg relative to the data edge. For more information on this function and others consult the SPI Doc at www.analog.com.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers, the SPI SDIO / DCS and SPI SCLK / DFS pins can alternately serve as stand alone CMOS compatible control pins When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer. In this mode the SPI CSB chip select should be connected to AVDD, which will disable the serial port interface.
Table 6. Mode Selection
Pin SPI SDIO / DCS SPI SCLK / DFS External Voltage AVDD AGND AVDD AGND Configuration Duty Cycle Stabilizer Enabled Duty Cycle Stabilizer Disabled 2's Complement Enabled Offset Binary Enabled
OPEN LOCATIONS
All locations marked as "open" are currently not supported for this particular device. When required, these locations should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x14). If the whole address location is open (for example, Address 0x13), then this address location does not need to be written.
DEFAULT VALUES
Coming out of reset, some of the address locations (but not all) are loaded with default values. The default values for the registers are given in the Table X.
LOGIC LEVELS
An explanation of various registers, "bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." Similarly "clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit."
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations. The memory map is roughly divided into four sections: chip
Figure X. Serial Port Interface Timing Diagram
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AD9211
Table X. AD9211 Device Configuration Register Memory Map
Preliminary Technical Data
.
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Preliminary Technical Data OUTLINE DIMENSIONS
a
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 x 8 mm Body, Very Thin Quad (CP-56-2) Dimensions shown in millimeters 0.30 0.23 0.18
56 1
AD9211
8.00 BSC SQ
0.60 MAX 0.60 MAX
43 42
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
7.75 BSC SQ
EXPOSED PAD (BOTTOM VIEW)
4.45 4.30 SQ 4.15
0.50 0.40 0.30
29 28
14 15
0.30 MIN 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
112805-0
6.50 REF
SEATING PLANE
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
Figure 16. Mechanical Drawing (Subject to change)
ORDERING GUIDE
Model AD9211BCPZ-1701 AD9211BCPZ-2001 AD9211BCPZ-2501 AD9211-250EB AD9211-200EB AD9211-170EB Temperature Range -40C to +85C -40C to +85C -40C to +85C 25C 25C 25C Package Description 56-Lead Lead Frame Chip Scale Package (LFCSP-VQ) 56-Lead Lead Frame Chip Scale Package (LFCSP-VQ) 56-Lead Lead Frame Chip Scale Package (LFCSP-VQ) LVDS Evaluation Board with AD9211BCPZ-250 LVDS Evaluation Board with AD9211BCPZ-200 LVDS Evaluation Board with AD9211BCPZ-170 Package Option CP-56 CP-56 CP-56
1
Z=Pb-free part
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. PR06041-0-3/06(PrA)
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